1. Field of the Invention
The present invention relates to a framing circuit and, in particular, to a framing circuit that removes an undesirably narrow clock pulse that results from an asynchronous frame boundary realignment.
2. Discussion of the Related Art
A framing circuit is a circuit that converts the data in a serial data bit stream into a series of parallel data words by continuously identifying n-bit framing bytes within the serial data bit stream, and then latching each successive frame of n-bits that follow the framing byte. In a conventional framing circuit, the framing byte is utilized to reset a byte clock signal which, in turn, is utilized in the remainder of the circuit to identify the beginning of each frame of data.
FIG. 1 shows a block diagram that illustrates a conventional framing circuit 10. As shown in FIG. 1, framing circuit 10 utilizes a standard shift register 12 to extract a series of n-bit data bit patterns PAT from the serial data bit stream, and a comparator 14 to compare each n-bit data bit pattern PAT to a predefined data bit pattern. In addition, framing circuit 10 also utilizes a clocking circuit 16 to output a byte clock signal BCLK, and a latch 18 to hold the parallel data words output from shift register 12.
In operation, shift register 12 outputs a continuous stream of n-bit data bit patterns PAT in response to a system clock signal SYSCLK. Comparator 14 receives each of these n-bit data bit patterns PAT and compares each pattern PAT with the predefined data bit pattern. When one of the n-bit data bit patterns PAT matches the predefined data bit pattern, comparator 14 outputs a framing signal FRM which indicates that a framing byte has been identified.
The framing signal FRM is utilized by clocking circuit 16 to reset the byte clock signal BCLK which, in turn, realigns the byte clock signal BCLK with the leading edge of the framing byte. As a result of this realignment, each subsequent frame of data can be identified by the byte clock signal BCLK. Thus, as shown in FIG. 1, the byte clock signal BCLK can be utilized by latch 18 to latch each subsequent frame of data output by shift register 12.
One problem with conventional framing circuits, however, is that each time the byte clock signal is reset to a first logic state immediately after transitioning to a second logic state, the pulse width of the byte clock signal is significantly reduced. This short pulse clock signal, in turn, can cause metastable conditions in the devices which utilize the byte clock signal.
As a result, there is a need for a framing circuit which will not produce a short pulse clock signal when the byte clock signal is reset to a first logic state immediately after transitioning to a second logic state.